This relates to solid-state image sensor arrays and, more specifically, to image sensors with small-size pixels that are illuminated from the back side of a pixel substrate. Small pixel sizes reduce the cost of manufacturing image sensor arrays, but it is important not to sacrifice image sensor performance when pixel size is reduced.
Typical complementary metal-oxide-semiconductor (CMOS) image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. Upon completion of each integration cycle, the collected charge is converted into voltage signals, which are supplied to corresponding output terminals associated with the image sensor. Typically, the charge-to-voltage conversion is performed directly within the pixels, and the resulting analog pixel voltage signals are transferred to the output terminals through various pixel addressing and scanning schemes. The analog voltage signal can sometimes be converted on-chip to a digital equivalent before being conveyed off-chip. Each pixel includes a buffer amplifier (i.e., source follower) that drives output sensing lines that are connected to the pixels via respective address transistors.
After the charge-to-voltage conversion is completed and after the resulting signals are transferred out from the pixels, the pixels are reset before a subsequent integration cycle begins. In pixels that include floating diffusions (FD) serving as the charge detection node, this reset operation is accomplished by momentarily turning on a reset transistor that connects the floating diffusion node to a voltage reference for draining (or removing) any charge transferred onto the FD node. However, removing charge from the floating diffusion node using the reset transistor generates thermal kTC-reset noise, as is well known in the art. This kTC reset noise must be removed using correlated double sampling (CDS) signal processing techniques in order to achieve desired low noise performance. Typical CMOS image sensors that utilize CDS require at least four transistors (4T) per pixel. An example of the 4T pixel circuit with a pinned photodiode can be found in Lee (U.S. Pat. No. 5,625,210), incorporated herein as a reference.
One primary disadvantage of conventional CMOS image sensors is that pixel scanning after charge has been accumulated in the pixels is performed in a sequential manner row-by-row. This generates exposure time skew, which is often observed as distortion in images of moving objects. Scanning the pixels row-by-row is referred to as operating the sensor in a “rolling shutter” mode, which resembles the action of a focal plane slit shutter found in conventional photographic film cameras. In most applications, however, it is preferable to expose all of the pixels of the array at the same time without exposure time skew to thereby eliminate distortion of moving objects in the image. This type of image sensor operation is referred to as “global shuttering” (GS) which resembles the operation of a mechanical iris shutter in conventional photographic film cameras. In order to implement this type of global shuttering, it is necessary to provide multiple charge storage sites in each sensor pixel.
After charge is integrated in photodiodes of the pixels when operating in a GS scheme, charge is transferred to pixel storage sites simultaneously in all of the pixels of the array, where charge can wait for scanning in a row-by-row fashion. The pixel scanning time skew is thus independent of the frame pixel exposure time. Examples of methods for incorporating multiple charge storage sites into the CMOS sensor pixels can be found in Yasutomi et al. (ISSCC Digest of Technical Papers, Feb. 10, 2010, pp. 398 and 399, entitled “A 2.7e Temporal Noise 99.7% Shutter Efficiency 92 dB Dynamic Range CMOS Image Sensor with Dual Global Shutter Pixels”), which is incorporated herein as a reference. The arrangement of Yasutomi et al. is a modification of the conventional Interline Transfer Charge Coupled Device (CCD) concept where charge from the pixel photodiodes is transferred first into vertical CCD registers located in the spaces between the pixels, and then from there charge is transferred in parallel fashion row-by-row into a serial register followed by a CCD charge transfer into a common single charge detection node and output amplifier. This application of the CCD charge transfer concept into CMOS sensors to implement global shuttering is shown in FIG. 1, where charge is stored in an additional pinned diode.
FIG. 1 shows a simplified circuit diagram of a pixel 100 in a CMOS sensor that has global shuttering capabilities. After charge integration is completed in first pinned photodiode 101, charge is transferred via charge transfer transistor 103 to second pinned diode 102. The transferred charge waits in diode 102 for scanning The charge transfer from first diode 101 to second diode 102 is complete in a CCD fashion without generating kTC noise. It is also necessary that either second diode 102 has a higher pinning voltage than diode 101, or transfer gate 103 has a potential barrier and a potential well. Moreover, it is necessary that the second diode 102 is well shielded from impinging photons 115 (i.e., the photons used to generate charge at first diode 101) to prevent undesirable smear effects when objects in the imaged scene move. The light shielding effect is characterized in such image sensors by a parameter referred to as shutter efficiency.
Signal charge readout operations form second diode 102 proceeds in a conventional manner by first resetting floating diffusion (FD) node 104 to drain bias voltage Vdd by momentarily turning on reset transistor 106, followed by pulsing the gate of charge transfer transistor 105. This sequence can now proceed in a sequential order row-by-row through the array. The signal appearing on floating diffusion 104 is buffered by source follower transistor 107 that is addressed by row addressing transistor 108. The pulses to control transfer transistor gates 103 and 105, reset transistor 106, and addressing transistor 108 are supplied by row bus lines 111, 112, 113, and 114, respectively (i.e., coupled to row control circuitry in the image sensor). Bias voltage Vdd is supplied to the pixels by column Vdd line 109 and the signal output appears on the column output line 110. Using the pinned diodes for charge storage in this way is advantageous because the diodes of this type have relatively low dark current generation characteristics (high levels of dark current in the charge storage regions can add noise and generate undesirable shading effects in the image). However, second diode 102 consumes a significant amount of pixel area, thus increasing the size of the corresponding image sensor and, ultimately, its cost. Another disadvantage of the pinned photodiode storage approach is the higher pinning voltage necessary for second diode 102 relative to the pinning voltage for diode 101. This higher pinning voltage consumes a valuable allocated voltage swing that is determined by the maximum device operating voltage and results in reduction of charge storage capacity, and thus the dynamic range (DR) of the image sensor.
The above-noted problems in the design of global shuttered pixels can be partially overcome in Front Side Illumination (SFI) applications, where a light shield can be placed over second pinned charge storage diode 102 to prevent light leakage into diode 102. However, such methods are counterproductive in Back Side Illumination (BSI) applications. In particular, a light shield placed on the back side of the sensor substrate in a BSI application is less efficient than in front side applications and limits the quantum efficiency (QE) of the sensor (a high quantum efficiency is a primary purpose for using back side illumination in small size pixel sensors). Therefore, it is not viable to use second pinned diode 102 for charge storage in a BSI application.
It would therefore be desirable to be able to provide improved back side illuminated image sensor pixels with global shutter capabilities.